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Integrated Mixed-Signal Solutions
STIr4200
USB/IrDA Bridge Controller
Version 2.0 April `03
OFFICIAL PRODUCT DOCUMENTATION
3-4200-D1-2.0-0403
Copyright (c) 2003 SigmaTel, Inc. All rights reserved. All contents of this document are protected by copyright law and may not be reproduced without the express written consent of SigmaTel, Inc. SigmaTel, the SigmaTel logo, and combinations thereof are registered trademarks of SigmaTel, Inc. Other product names used in this publication are for identification purposes only and may be trademarks or registered trademarks of their respective companies. The contents of this document are provided in connection with SigmaTel, Inc. products. SigmaTel, Inc. has made best efforts to ensure that the information contained herein is accurate and reliable. However, SigmaTel, Inc. makes no warranties, express or implied, as to the accuracy or completeness of the contents of this publication and is providing this publication "AS IS". SigmaTel, Inc. reserves the right to make changes to specifications and product descriptions at any time without notice, and to discontinue or make changes to its products at any time without notice. SigmaTel, Inc. does not assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential, or incidential damages.
OFFICIAL
PRODUCT
DOCUMENTATION
STIr4200
USB/IrDA Bridge Controller 1. TABLE OF CONTENTS
1. TABLE OF CONTENTS .............................................................................................. 2
1.1. List of Figures .................................................................................................................... 3 1.2. List of Tables .....................................................................................................................3
2. PRODUCT OVERVIEW ............................................................................................... 4
2.1. Features ............................................................................................................................ 4 2.2. Description ........................................................................................................................ 4 2.3. Ordering Information ......................................................................................................... 4 2.4. STIr4200 Block Diagram .................................................................................................. 5
3. CHARACTERISTICS AND SPECIFICATIONS ........................................................... 5
3.1. Absolute Maximum Ratings .............................................................................................. 5 3.2. Recommended Operating Conditions ............................................................................... 5 3.3. Electrical Characteristics ................................................................................................... 6
4. FUNCTIONAL DESCRIPTION .................................................................................... 6
4.1. Overview ...........................................................................................................................6 4.2. USB Interface .................................................................................................................... 7 4.3. Vendor-Specific Device Requests ..................................................................................... 7 4.3.1. Write Multiple Registers ....................................................................................... 7 4.3.2. Write One Register ............................................................................................... 7 4.3.3. Read Multiple Registers ....................................................................................... 8 4.3.4. Read ROM ........................................................................................................... 8 4.3.5. Vendor Clear Stall ................................................................................................ 8 4.4. Digital IR Transceiver ........................................................................................................9 4.5. FIFO Contents ................................................................................................................... 9
5. IR FRAMING FORMATS ........................................................................................... 10
5.1. Transmit Frame Format ..................................................................................................10 5.1.1. SIR Transmit Frame ...........................................................................................10 5.1.2. FIR Transmit Frame ...........................................................................................11 5.1.3. Receive Frame Format .......................................................................................12 5.1.3.1. SIR Receive Frame ............................................................................12 5.1.3.2. FIR Receive Frame ............................................................................13
6. DIGITAL IR TRANSCEIVER REGISTERS ................................................................ 14
6.1. Detailed STIr4200 Register Descriptions .......................................................................14 6.1.1. FIFO Data Register ............................................................................................14 6.1.2. Mode and Baud Rate Registers .........................................................................15 6.1.2.1. Mode Register ....................................................................................15 6.1.2.2. Baud Rate Register ............................................................................15 6.1.3. Control Register .................................................................................................16 6.1.4. Sensitivity Register .............................................................................................17 6.1.5. Status Register ...................................................................................................17 6.1.6. FIFO Count Registers (LSB,MSB) .....................................................................18 6.1.6.1. FIFO Count LSB .................................................................................18 6.1.6.2. FIFO Count MSB ................................................................................18 6.1.7. DPLL Tune Register ...........................................................................................18 6.1.8. IRDIG Setup Register .........................................................................................19 6.1.9. Test Register ......................................................................................................19
7. PIN DESCRIPTION .................................................................................................... 20
7.1. STIR4200S 28-Pin SSOP Pin Description .......................................................................20
8. PACKAGE DRAWINGS ............................................................................................ 21
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USB/IrDA Bridge Controller 1.1. List of Figures
Figure 1. STIr4200 Block Diagram .................................................................................................5 Figure 2. Typical USB-IR Application ............................................................................................. 6 Figure 3. Block Diagram of Digital IR Transceiver .......................................................................... 9 Figure 4. SIR Transmit Frame Format ..........................................................................................10 Figure 5. FIR Transmit Frame Format ..........................................................................................11 Figure 6. SIR Receive Frame Format ...........................................................................................12 Figure 7. FIR Receive Frame Format ...........................................................................................13 Figure 8. STIR4200S 28-Pin SSOP Pin Assignment Drawing .......................................................20 Figure 9. 28-Pin SSOP Package Drawing ....................................................................................21
1.2.
List of Tables
Table 1. Absolute Maximum Ratings .............................................................................................. 5 Table 2. Recommended Operating Conditions ..............................................................................5 Table 3. Electrical Characteristics .................................................................................................. 6 Table 4. Write Multiple Registers .................................................................................................... 7 Table 5. Write One Register ........................................................................................................... 7 Table 6. Read Multiple Registers ................................................................................................... 8 Table 7. Read ROM ........................................................................................................................ 8 Table 8. Vendor Clear Stall ............................................................................................................ 8 Table 9. IrLAP Frame .....................................................................................................................9 Table 10. Ir Transceiver Registers ...............................................................................................14 Table 11. FIFO Data Register ......................................................................................................14 Table 12. Mode Register ..............................................................................................................15 Table 13. Baud Rate Register ......................................................................................................15 Table 14. Mode and Buad Rate Values for Required IrDA Modes of Operation ..........................15 Table 15. Control Register ............................................................................................................16 Table 16. Sensitivity Register .......................................................................................................17 Table 17. Status Register .............................................................................................................17 Table 18. FIFO Count LSB ...........................................................................................................18 Table 19. FIFO Count MSB ..........................................................................................................18 Table 20. DPLL Tune Register .....................................................................................................18 Table 21. IRDIG Setup Register ...................................................................................................19 Table 22. Test Register ................................................................................................................19 Table 23. Pin Descriptions for STIR4200S 28-Pin SSOP Package ...............................................20
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STIr4200
USB/IrDA Bridge Controller 2. PRODUCT OVERVIEW 2.1. Features
* * * * * * * * * * Low-power CMOS design IrDA data rates from 2.4 Kbps to 4 Mbps Obtains power from USB port Uses standard IrDA transceivers Optional LED driver for additional flexibility - LED driver capable of > 650 ma @ 5V, 25% duty cycle Full compliance to IrDA 1.3 and USB 1.1 specifications 4 Kbyte FIFO buffer memory Requires a single 12 Mhz crystal Windows 98/98SE/ME/2000/XPTM NDIS/USB driver Low-profile 28-Pin SSOP package
2.2.
Description
The SigmaTel STIr4200 is a low cost, low power, USB/IrDA Bridge Controller integrated circuit for enabling IrDA wireless data communications through a standard PC USB port. The STIr4200 directly interfaces to both single path and dual path receive IrDA transceiver module architectures and contains a USB controller, IrDA controller, interface logic, and memory buffer for full IrDA 1.3, 4 Mbps data transfer rates. A block diagram is hown in Figure 1. The STIr4200 is bundled with a Windows 98/98SE/ME/2000/XPTM NDIS/USB driver for enabling the implementation of a cost effective USB/IrDA Adapter solution for wireless data communications.
Infrared Communication Transmission
Infrared Transceiver
SigmaTel USB/ IrDA Bridge Controller
Data Transfer
USB Connection to the PC
2.3.
Ordering Information
Package 28-Pin SSOP Temp Range 0 C to +70 C Supply Range Vdd = 3.1 - 3.6V
Part Number STIR4200S
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USB/IrDA Bridge Controller 2.4. STIr4200 Block Diagram
Optional LED Driver TX DIODE
USB - IRDA Bridge IC
USB - IRDA Interface Logic
USB Port
USB Controller Bulk In
IrDA Controller UOUT 4K FIFO Buffer IrDA Digital Interface TXDATA
IrDA Transceiver Interface SD/MODE (TEMIC ONLY) TXD
D POS
USB Port Interface
+V
Bulk Out
D NEG Gnd
Control
IR Register Set
RXFAST
RXD/R XFAST
RXSLOW RXSLOW (DUAL RECEIVE PATH)
12 Mhz
Figure 1. STIr4200 Block Diagram
3. CHARACTERISTICS AND SPECIFICATIONS 3.1.
Symbol PD TA TJ TS VCC Vmax
Absolute Maximum Ratings
Parameter Power Dissipation (Package constraint) Operating Temperature Lead Solder Temperature Storage Temperature Supply Voltage Voltage at any pin -55 -0.3 V 0 70 260 125 6 VDD + 0.4V MIN MAX UNITS mW C C C V V for 10 sec max. CONDITIONS
ESD Electrostatic Discharge (ESD) +/- 2KV V See Note 1 Note: 1. The device meets the JESD22-A114-A Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) requirements of +/- 2KV on all pins, except the TXDIODE pin (Pin 2), where the limit is +/1.5KV. Table 1. Absolute Maximum Ratings
3.2.
Symbol VDD TA
Recommended Operating Conditions
Parameter Supply Voltage Operating Temperature Range MIN 3.1 0 TYP 3.3 25 MAX 3.6 70 UNITS V C CONDITION
Table 2. Recommended Operating Conditions
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USB/IrDA Bridge Controller 3.3.
Symbol ICC ICC VRXDH VRXDL VTXDH VTXDL
Electrical Characteristics
TA = 25CA VDD = 3.3V unless otherwise specified. Cap Load = 50pF
Parameter Active Supply Current Suspend Supply Current Receive Data Logic High Receive Data Logic Low Transmit Data Logic High Transmit Data Logic Low VDD x 0.6 VDD x 0.4 Table 3. Electrical Characteristics VDD x 0.8 0.8 MIN TYP 12 14 MAX 19 50 UNITS mA A V V V V CONDITION
4. FUNCTIONAL DESCRIPTION 4.1. Overview
The STIr4200 consists of two major functional blocks, the USB controller and the digital IR transceiver. The USB controller provides a Control, Bulk-In, and Bulk- Out endpoints to the USB host. The digital IR transceiver consists of a transmit and receive interface that connects to an analog IR front end. Figure 1shows a block diagram of the device. This USB/IrDA Bridge Controller has full interface capability to connect between a USB bus , and an IrDA-compatible infrared transceiver device. A simplified schematic of this arrangement is shown in Figure 2.
Voltage Regulator USB IrDA Transceiver USB Connector V+ DD+ GND Vcc
STIR4200S
USB-IrDA Bridge Controller
GND RXD TXD SD
Figure 2. Typical USB-IR Application
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USB/IrDA Bridge Controller 4.2. USB Interface
The USB interface to the host controller includes a Control endpoint, a Bulk-In endpoint, and a Bulk-Out endpoint. The USB controller supports the USB 1.1 specification. Hence, it supports all standard functionality associated with device enumeration, standard USB device requests, etc. In addition, there is a set of vendor specific commands provided to allow a USB driver to access registers in the Digital IR Transceiver and ROM in the USB controller. Note: The STIr4200 device conforms to all of the USB 1.1 specifications with one exception of the "get_interface" command. This command is used only during USB conformance testing, and during that testing, improper operation will be noted on test results. However, the software drivers provided by SigmaTel, Inc. do NOT use that command at all, and this does NOT cause any problem of any kind in operation. A waiver for this command has been obtained from USBIF by SigmaTel, Inc. This command is not used by the software, and therefore has no effect on device and system operation. The only time this "get_interface" command is even accessed is during USB conformance testing.
4.3.
Vendor-Specific Device Requests
4.3.1. Write Multiple Registers
The write multiple registers vendor specific command allows the user to write multiple sequential registers to the Digital IR Transceiver. Each register is one byte wide, so the command indicates first register to write, the number of registers to write, and the data phase supplies the data for those registers.
Offset 0 1 2 4 6 Field Brequest Wvalue Windex Wlength Data phase Size 1 2 2 2 Value (hex) 0x40 0x00 Not used (0x0000) 0x0001-0x000f 0x0001-0x000f First register to write Number of registers to write Description Host to device, vendor type, device recipient Write multiple registers bmRequestType 1
1-15 bytes of Register Data Table 4. Write Multiple Registers
4.3.2.
Write One Register
The write one register vendor specific command allows the user to write a single register to the Digital IR Transceiver.
Offset 0 1 2 4 6 Field Brequest Wvalue Windex Wlength Size 1 2 2 2 Value (hex) 0x40 0x03 0x0001 - 0x000f Description Host to device, vendor type, device recipient Write one register Register to write bmRequestType 1
LSB contains data The data to write the register Not used (0x0000) Table 5. Write One Register
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USB/IrDA Bridge Controller
4.3.3.
Read Multiple Registers
The read multiple registers vendor specific command allows the user to read multiple sequential registers from the Digital IR Transceiver. Each register is one byte wide, so the command indicates the first register to read, the number of registers to read, and the responding data phase supplies the data from those registers. This command is also used for the case of reading only one register.
Offset 0 1 2 4 6 Field BRequest Wvalue Windex Wlength Size 1 2 2 2 Value (hex) 0xc0 0x01 Not used (0x0000) 0x0001 - 0x000f First register to read 0x0001 - 0x000f Number of registers to read Table 6. Read Multiple Registers Description Device to host, vendor type, device recipient Read multiple registers bmRequestType 1
4.3.4.
Read ROM
The read ROM vendor specific command allows the user to read the contents of the USB controller endpoint zero ROM. This is primarily a debug feature that allows verification of the endpoint zero ROM contents. Only 64 bytes of ROM data can be requested at a time. The responding data phase supplies the data from the endpoint zero ROM.
Offset 0 1 2 4 6 Field Brequest Wvalue Windex Wlength Size 1 2 2 2 Value (hex) 0xc0 0x02 Not used (0x0000) 0x0000-0x00ff 0x01-0x0040 Base ROM address Number of ROM locations to read (64 bytes max per request) Table 7. Read ROM Read ROM Description Device to host, vendor type, device recipient BmRequestType 1
4.3.5.
Vendor Clear Stall
The vendor clear stall command is included as a potential work around for limitations in early versions of the MicrosoftTM USB driver stack. Although not a concern with the latest operating systems, the earlier versions could have the possibility that the USB driver stack would not properly clear endpoint stalls. The standard device clear stall request is also supported.
Offset 0 1 2 4 6 Field Size Value (hex) 0x42 0x01 Not used (0x0000) 0x0000 - 0x0002 Endpoint on which to clear stall Not used (0x0000) Table 8. Vendor Clear Stall Description Device to host, vendor type, endpoint recipient Clear endpoint stall BmRequestType 1 Brequest Wvalue Windex Wlength 1 2 2 2
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USB/IrDA Bridge Controller 4.4. Digital IR Transceiver
The Digital IR Transceiver is responsible for driving the transmit diode and receiving the digital input from an analog IR front end. The primary components are the transmit modulator, the receive demodulator, the FIFO, the analog transmit section, and the register array. Figure 3 shows a block diagram of the Digital IR Transceiver. By programming the registers in the register array, the device's operation is determined. Various registers are used to specify operations such as the modulation scheme, the baud rate, the current frame size in the FIFO, the RX input selection, etc. The FIFO is 4K bytes in size.
USB-IR Interface Logic
TX Modulator FIFO
(ASK, IrDA FIR,MIR,SIR)
USB Interface
Analog TX Section
TXDIODE TXDATA RXFAST RXSLOW
RX Demodulator
(ASK, IrDA FIR,MIR,SIR)
Register Array
Figure 3. Block Diagram of Digital IR Transceiver
In steady state transmit operation, the USB controller is filling the FIFO with data while the Digital IR Transceiver is emptying it via the transmit modulator. In steady state receive operation, the USB controller is emptying the FIFO while the RX demodulator is filling the FIFO.
4.5.
FIFO Contents
Data sent to the USB controller for transmission by the TX modulator must be organized into frames. An IrLAP frame is made up of the following portions:
BOF A BOF A C I FCS EOF C I FCS EOF
Beginning of frame(s) Address field Control field Information field Frame check sequence (CRC) End of frame Table 9. IrLAP Frame
The NDIS IR stack only provides the A, C, and I fields to the NDIS mini-port device driver that communicates with the USB/IrDA transceiver. Hence, the mini-port must fill in the BOF, FCS, and EOF fields. Additionally, the driver must add a 2-byte header ID code and a 2-byte frame size to the packet before passing the packet onto the USB stack for delivery to the USB/IrDA transceiver. There are additional special characters and required escape sequences depending upon the rate of transfer. Details on the frame format for each of the support rates is discussed in the following sections.
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USB/IrDA Bridge Controller 5. IR FRAMING FORMATS 5.1. Transmit Frame Format
5.1.1. SIR Transmit Frame
The SIR rates include 2.4, 9.6, 19.2, 38.4, 57.6, and 115.2 Kbps. For SIR, the frame presented to the USB bulk transmit interface must be organized in the following fashion as shown in Figure 4.
0x55 0xAA LSB size Number of following bytes MSB size 0xC0 0xC0 0xC0 0xC0 0xC0 ... Data Data Data Data Data Data Data ... LSB CRC MSB CRC 0xC1 FCS : 16 bit CRC-CCITT EOF - End of frame A C I Address/Control/Information Fields Special characters must be escaped Original Data Escaped Data 0xC0 0x7D 0xE0 0xC1 0x7D 0xE1 0x7D 0x7D 0x5D BOF = Beginning of frame characters The number of beginning of frame characters is determined during the negotiation stage. Header ID
Figure 4. SIR Transmit Frame Format
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USB/IrDA Bridge Controller
5.1.2. FIR Transmit Frame
The FIR rate is 4 Mbps The frame organization is detailed in Figure 5.
0x55 0xAA LSB size Number of following bytes MSB size 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7E 0x7E Data Data Data Data Data Data Data
Header ID
PREAMBLE : These characters cause the STIR4200S to generate the preamble sequence used by the receiving device for synchronization. There must be exactly 16 characters.
BOF = Beginning of frame
A C I Address/Control/Information Fields Special characters must be escaped Original Data Escaped Data 0x7D 0x7D 0x5D 0x7E 0x7D 0x5E 0x7F 0x7D 0x5F
LSB CRC

FCS : 32 bit CRC-IEEE802
MSB CRC 0x7E 0x7E EOF - End of frame
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USB/IrDA Bridge Controller
5.1.3. Receive Frame Format
Data received into the STIr4200 FIFO from the digital infrared interface can be accessed by performing a bulk read on the USB interface. The received data contains the encoded infrared data. The STIr4200 does not perform any frame validation or CRC-Checking. Multiple frames may exist within one bulk read depending upon the size of the bulk read. However, the end of the bulk read buffer may not necessarily coincide with the end of an infrared frame. It is highly likely that the data at the end of a bulk read will be a partial frame. The remaining frame data will be acquired in the next bulk read. The bulk data thus contains start-of-frame (BOF) characters, end-of-frame (EOF) characters, and escape characters that delineate the actual frame. It is the responsibility of the host software to reconstruct the frame.
5.1.3.1.
SIR Receive Frame
The standard SIR encoding scheme provides all information needed to delineate the encoded receive frames. Figure 6 summarizes the SIR receive frame format encoding scheme.
0xC0 0xC0 0xC0 0xC0 0xC0 ... Data Data Data Data Data Data Data ... LSB CRC MSB CRC 0xC1 FCS : 16 bit CRC-CCITT EOF - End of frame A C I Address/Control/Information Fields Special characters have been escaped. Software must un-escape the data Escaped Data Original Data Original Data 0x7D 0xE0 0xC0 0xC0 0x7D 0xE1 0xC1 0xC1 0x7D 0x5D 0x7D 0x7D BOF = Beginning of frame characters The number of beginning of frame characters is determined during the negotiation stage.
Figure 6. SIR Receive Frame Format
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USB/IrDA Bridge Controller
5.1.3.2. FIR Receive Frame
The FIR encoding scheme is modified slightly from the standard scheme. The character 0x7E is used to delineate the BOF and EOF. The STIr4200 escapes three characters in the data field on receive, 0x7F, 0x7E and 0x7D, which allows the 0x7E characters used as BOF and EOF to be unique. The 0x7E character can then be used to delineate the infrared frame boundaries. This hardware escaping in the data portion is specific to the STIr4200, and the software must un-escape the data portion of the received frame to restore the original data. Figure 7 summarizes the FIR receive frame format encoding scheme.
0x7E 0x7E Data Data Data Data Data Data Data Data ... LSB CRC ... A C I Address/Control/Information Fields Special characters must be un-escaped Escaped Data Original Data 0x7D 0x5D 0x7D 0x7D 0x5E 0x7E 0x7D 0x5F 0x7F BOF = Beginning of frame
...
MSB CRC 0x7E 0x7E
FCS : 32 bit CRC-IEEE802
EOF - End of frame
Figure 7. FIR Receive Frame Format
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USB/IrDA Bridge Controller 6. DIGITAL IR TRANSCEIVER REGISTERS
Offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Description FIFO Data Mode Register Baud Rate Register Control Register Sensitivity Register Status Register FIFO Count (Note 1) Register (LSB) FIFO Count (Note 1) Register (MSB) DPLL Tune Register IRDIG Setup Register Reserved Reserved Reserved Reserved Reserved Test Register RO RO RO R/W R/W R/W R/W R/W R/W R/W PLLDWN RXHIGH TXLOW 0 0 0 DPCNT(5: 0) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved LOOPIR LOOPUSB TSTENA TSTOSC(3: 0) Access 7 R/W R/W R/W R/W SDMODE RXSLOW DLOOP1 RXDSNS(2: 0) EOFRAME FFUNDER FFOVER RO ROC ROC FIR Reserved SIR 6 5 Bit Position 4 Reserved ASK TXPWD FASTRXEN FFRSTEN FFSPRST PDCLK(8) RXPWD TXPWR(1: 0) ID(2) RO ID(1) RO SRESET ID(0) RO PDCLK(7: 0) BSTUFF SPWIDTH R/W R/W FFDIR RO FFCLR WO 3 2 1 0
FFEMPTY FFRXERR FFTXERR RO ROC ROC
FFCNT(7:0) FFCNT(12: 8) LONGP(1: 0) Reserved Reserved Reserved
R/W : Read/Write RO : Read only ROC : Read only, clear on read WO : Write only
Note:
1.
Due to double buffering, FFCNT could be off by as much as 3 bytes Table 10. Ir Transceiver Registers
6.1.
Detailed STIr4200 Register Descriptions
6.1.1.
7
FIFO Data Register
Offset 0
6 0 Access R/W 5 0 4 0 3 Reserved 0 0 0 Function The FIFO data register is used internally by the USB interface to access the FIFO data in the digital infrared block. Although this register is accessible through the USB interface, it should never be accessed during normal operation. 0 0 2 1 0
FIFO Data Default State Bit Number 7-0
Bit Mnemonic Reserved
Table 11. FIFO Data Register
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6.1.2. Mode and Baud Rate Registers
Offset 1 and 2
6.1.2.1.
Offset 1
7 Mode Register Default State FIR 0
Mode Register
6 Reserved 0 5 SIR 1 4 ASK 0 3 0 Function When set, puts the infrared modulators into fast infrared mode (4PPM). Must be mutually exclusive with the SIR bit. Reserved. Write as zero. When set, puts the infrared modulators into slow infrared mode. Must be mutually exclusive with the FIR bit. When set, puts the infrared modulators into amplitude shift keying infrared mode. Enables simultaneous reads and writes to/from the FIFO. Allows the FIFO receive shift register to be automatically reset in FIR mode. Manually resets the FIFO shift register. Must be set to `1' to release the FIFO shift register from reset. MSB of baud rate register. Table 12. Mode Register 2 0 1 0 0 0
FASTRXEN FFRSTEN FFSPRST PDCLK(8)
Bit Number Bit Mnemonic Access 7 6 5 4 3 2 1 0 FIR Reserved SIR ASK FASTRXEN FFRSTEN FFSPRST PDCLK(8) R/W RO R/W R/W R/W R/W R/W R/W
6.1.2.2.
Offset 2
7 Baud Rate Register Default State 0
Baud Rate Register
6 1 5 1 4 3 2 1 1 1 0 1
PDCLK(7: 0) 1 0 Function
Bit Number Bit Mnemonic Access 7:0 PDCLK (7 : 0) R/W
Sets the divide ratio of the PLL for the infrared modulator/demodulator. Table 13. Baud Rate Register
Below is a table of values to be written to the mode and baud rate registers to set the required IrDA modes of operation:
Operational Mode FIR Speed 4.0 Mbps 115.2 Kbps 57.6 Kbps SIR 38.4 Kbps 19.2 Kbps 9.6 Kbps 2.4 Kbps Mode Register 0x80 0x20 0x20 0x20 0x20 0x20 0x21 Baud Rate Register 0x02 0x09 0x13 0x1D 0x3B 0x77 0xDF
Table 14. Mode and Buad Rate Values for Required IrDA Modes of Operation
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USB/IrDA Bridge Controller
6.1.3. Control Register
Offset 3
7 Control Register Default State SDMODE 0 6 RXSLOW 0 5 Reserved 0 4 TXPWD 0 3 RXPWD 0 Function Use this bit only when the STIr4200 is connected to a TEMIC style infrared transceiver. This bit is used to put the infrared transceiver into the power down state or toggle the transceiver between high and low speed. POWER DOWN STATE: Set the SD/MODE bit to enter the power down state. Clear the SD/MODE bit to exit the power down state. SET TEMIC HIGH SPEED: Set the FIR bit (bit 7) in the Mode Register, then set SD/MODE bit, then clear SD/MODE bit. SET TEMIC LOW SPEED: Clear the FIR bit (bit 7) in the Mode Register, then set the SD/MODE bit, then clear the SD/MODE bit. The sequences described above for setting the high or low speed mode enables a state machine in the STIr4200 to automatically toggle the TXDATA and UOUT (SD/MODE) pins on the STIr4200. When set, selects RXSLOW as the receive input. When cleared, selects RXFAST as the receive input. Reserved When set, powers down the infrared transmitter (modulator). When set, powers down the infrared receiver (demodulator). Sets the internal pull down resistance to control the current presented to the transmit diode. 00 : HIGH (max current) 01 : MED HIGH 10 : MED LOW 11 : LOW (min current) When set, performs soft reset of the infrared modulator/demodulator. Table 15. Control Register 2 0 1 0 0 SRESET 0 TXPWR(1: 0)
Bit Number Bit Mnemonic Access 7 SD/MODE R/W
6 5 4 3 2-1
RXSLOW Reserved TXPWD RXPWD TXPWR(1: 0)
R/W R R/W R/W R/W
0
SRESET
R/W
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USB/IrDA Bridge Controller
6.1.4. Sensitivity Register
Offset 4
7 Sensitivity Register Default State 0 6 RXDSNS(2: 0) 0 1 5 4 Reserved 0 3 SPWIDTH 0 Function Used to program the sensitivity of the DRS demodulator. The corresponding samples is the number of consecutive samples of an IrDA pulse it takes the digital detector to declare the presence of a valid IrDA pulse. Value 000 001 010 011 100 101 110 111 4 3 2-0 Note: 1. Reserved SPWIDTH RO R/W Reserved. Write as zero. SIR transmit pulse width. When cleared, the pulse width for SIR mode transmission is 1.6usec. When set, the pulse width is 3/16th the bit rate. FIR 1 2 3 4 5 Illegal Illegal Illegal SIR 4 8 12 16 20 24 28 Illegal ID(2) 2 1 ID(2: 0) ID(1) ID(0) 0
Bit Number Bit Mnemonic Access 7-5 RXDSNS(2: 0) R/W
ID(2: 0) (Note 1) RO Revision ID of the chip. For LA9 device revision, ID (2::0) = 1 1 1 Table 16. Sensitivity Register
6.1.5.
Status Register
Offset 5
7 6 Reserved 0 5 4 FFDIR 1 3 FFCLR 0 Function Reserved When set, the FIFO is in transmit mode. When cleared, the FIFO is in receive mode. When set, clears the FIFO by resetting the pointers to the empty position. This bit must then be cleared to enable operation of the FIFO. Failing to do so, will prohibit operation of the FIFO. The state of the bit can not be read. When set, indicates there is no data in the FIFO. Reserved Table 17. Status Register 2 FFEMPTY 1 1 Reserved 0 0
Status Register Default State
Bit Number Bit Mnemonic Access 7-5 4 3 Reserved FFDIR FFCLR N/A RO WO
2 1-0
FFEMPTY Reserved
RO N/A
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STIr4200
USB/IrDA Bridge Controller
6.1.6. FIFO Count Registers (LSB,MSB)
Offset 6&7
6.1.6.1.
Offset 6
7 FIFO Count Register (LSB) Default State 0
FIFO Count LSB
6 0 5 0 4 0 3 0 Function When combined with the FIFO Count Registers (MSB), indicates the number of bytes in the FIFO. Table 18. FIFO Count LSB 2 0 1 0 0 0
FFCNT(7: 0)
Bit Number Bit Mnemonic Access 7-0 FFCNT(7:0) RO
6.1.6.2.
Offset 7
7 FIFO Count Register (MSB) Default State 0
FIFO Count MSB
6 Reserved 0 0 0 0 Function Write as zeros. When combined with the FIFO Count Registers (LSB), indicates the number of bytes in the FIFO. Table 19. FIFO Count MSB 5 4 3 2 FFCNT(12: 8) 0 0 0 1 0
Bit Number Bit Mnemonic Access 7-5 4-0 Reserved FFCNT(12:8) RO RO
6.1.7.
DPLL Tune Register
Offset 8
7 6 1 5 0 4 1 3 0 Function Sets the sensitivity of the receiver's digital PLL. This bit should be used for chip debug purposes only. This register setting only affects FIR mode. The default setting is proper for normal operation. Sets the sensitivity of the pulse detector of the receiver. These bits should be used for chip debug purposes only. Table 20. DPLL Tune Register 2 0 1 1 0 0
DPLL Tune Register Default State 0
DPCNT(5: 0)
LONGP(1: 0)
Bit Number Bit Mnemonic Access 7-2 DPCNT(5: 0) R/W
1-0
LONGP(1: 0)
R/W
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STIr4200
USB/IrDA Bridge Controller
6.1.8. IRDIG Setup Register
Offset 9
7 IRDIG Setup Register Default State 0 6 0 5 4 3 Reserved 0 Function When set, this bit inverts the polarity of the data received by the digital interface on the RXFAST and RXSLOW pins. When set, this bits inverts the polarity of the data transmitted by the digital interface on the TXDATA pin. Reserved 2 1 0 RXHIGH TXLOW
Bit Number Bit Mnemonic Read/Write Access 7 6 5-0 RXHIGH TXLOW Reserved R/W R/W R/W
Table 21. IRDIG Setup Register
6.1.9.
7 Test Register Default State
Test Register
Offset 15
6 LOOPIR 0 5 LOOPUSB 0 4 Reserved 0 0 3 2 0 Function When set, powers down the secondary infrared transceiver PLL. This bit should be cleared for SIR operation. Two independent PLLs are required in this mode of operation. This bit should be set for FIR operation since the infrared transceiver uses the USB PLL in this mode of operation. When set, puts the infrared transceiver into internal loop back using the FIFO to buffer data. This bit should be used for chip debug purposes only. When set, puts the USB interface into loop back mode using the FIFO to buffer data. This bit should be used for chip debug purposes only. Enables the oscillator to be powered down while in USB Suspend Mode. Sets the bias currents for the crystal oscillator circuitry. These bits should be used for chip debug purposes only. Table 22. Test Register 1 0 0 0
PLLDWN 0
TSTOSC(3 : 0)
Bit Number Bit Mnemonic Read/Write Access 7 PLLDWN R/W
6
LOOPIR
R/W
5
LOOPUSB
R/W
4 3-0
TSTENA TSTOSC(3: 0)
R/W R/W
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STIr4200
USB/IrDA Bridge Controller 7. PIN DESCRIPTION 7.1. STIR4200S 28-Pin SSOP Pin Description
TXDIODE GND TXDIODE N/C N/C RXFAST TXDATA RXSLOW UOUT DIGITAL GND VDD ANALOG GND DNEG N/C N/C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23
N/C N/C XTALO XTALI GND D RESET Z TST_EN TST D TST-CLK UIN VDA DPOS N/C N/C
STIR4200S
28-Pin SSOP
22 21 20 19 18 17 16 15
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Note: "N/C" indicates the pin is "not connected" Figure 8. STIR4200S 28-Pin SSOP Pin Assignment Drawing Signal Name Type Description PWR TXDIODE power supply ground TXDIODE GND TXDIODE O Optional LED driver output NC No connect NC No connect RXFAST I Receive data from IR module (Fast) TXDATA O Transmit data output to IR module RXSLOW I Receive data from IR module (Slow) UOUT O SD/Mode control to IR module DGND PWR Digital power supply ground VDD PWR Digital power supply (+) AGND PWR USB transceiver power supply ground DNEG I/O USB interface negative (-) data NC No connect NC No connect NC No connect NC No connect DPOS I/O USB interface positive (+) data VDA PWR USB transceiver power supply (+) UIN I/O Test TST-CLK I Test clock input TSTD I/O Test data input/output TST_EN I Test enable RESETZ I Master reset, active low GNDD PWR Power supply ground XTALI I 12Mhz crystal/clock input XTALO O 12Mhz crystal/clock output NC No connect NC No connect Table 23. Pin Descriptions for STIR4200S 28-Pin SSOP Package
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STIr4200
USB/IrDA Bridge Controller 8. PACKAGE DRAWINGS
Figure 9. 28-Pin SSOP Package Drawing
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